1. Field of the Invention
The present invention relates to isolation techniques in semiconductor integrated circuits, and more particularly, to isolation techniques in silicon-on-insulator integrated circuits and isolation of radio frequency (RF) signals in silicon-on-insulator integrated circuits.
2. Description of the Related Art
In semiconductor electronics, the general trend is smaller and smaller form factors with improved performance and lower cost. In order to reduce form factors, more circuitry must be packed into less wafer real estate. As inter-device spacing shrinks, at some point adjacent elements of the circuitry begin to interact with each other, reducing their performance. The basic measurement parameter that characterizes this effect is called isolation. High isolation, and in particular, high RF isolation, implies that devices can be spaced closer together, and die size is minimized. Minimum size in turn implies placement in smaller packaging and less space used on the application PCB Board. Also, since wafer processing costs are nearly independent of the chip size, smaller circuits imply more die per wafer and thus a lower per die cost.
Isolation is a key parameter particularly important for analog integrated circuits (ICs). For example, isolation is important for ICs used in wireless communications applications. In general, wireless communications devices use high-frequency signals: 900 MHz to 1900 MHz for cellular phones and higher (up to 6 GHz) for other systems, such as wireless LANs. The proposed Bluetooth standard calls for operation in the unlicensed ISM band at 2.4 GHz. Signals at such frequencies, i.e., high radio frequencies (RF), are difficult to generate and control. They also have a tendency to interfere with each other, as they are easily coupled by parasitic properties present in all electronic components, including ICs. In ICs, many of the undesirable parasitic effects result from the conductive silicon substrate on which the circuits are fabricated. Poor isolation in a receiver, for example, can lead to an amount of local oscillator (LO) signal appearing at the output of the receiver and effectively be transmitted at the antenna. Wireless regulatory authorities limit the amount of spurious signal that can be radiated by the receiver, so limiting the amount of LO radiation is necessary to meet these specifications.
One type of semiconductor technology that is finding more use in bipolar applications is Silicon-On-Insulator (SOI). With SOI, an insulating layer separates circuit devices from the solid silicon substrate. An example of one particular SOI technology is the bonded SOI BiCMOS process technology that is available from Hitachi Ltd. of Japan, and specifically, the Hitachi Ltd. Device Development Center in Tokyo, Japan. This SOI BiCMOS process technology is also described in U.S. Pat. No. 5,661,329 entitled xe2x80x9cSemiconductor Integrated Circuit Device Including An Improved Separating Groove Arrangementxe2x80x9d, U.S. Pat. No. 5,773,340 entitled xe2x80x9cMethod of Manufacturing a BIMISxe2x80x9d, and U.S. Pat. No. 5,430,317 entitled xe2x80x9cSemiconductor Devicexe2x80x9d, the complete disclosures of which are all hereby fully incorporated into the present application by reference. Furthermore, this SOI BiCMOS process technology is also described in the paper entitled xe2x80x9cA 0.35 um ECL-CMOS Process Technology on SOI for 1 ns Mega-bits SRAM""s with 40 ps Gate Arrayxe2x80x9d by T. Kikuchi, Y. Onishi, T. Hashimoto, E. Yoshida, H. Yamaguchi, S. Wada, N. Tamba, K. Watanabe, Y. Tamaki, and T. Ikeda of the Hitachi Ltd. Device Development Center, Tokyo, Japan, published in the IEDM Technical Digest, IEDM 95-923, in connection with the International Electron Devices Meeting, Dec. 10-13, 1995, 0-7803-2700-4, 1995 IEEE, the complete disclosure of which is hereby fully incorporated into the present application by reference. An SOI process technology is also described in the paper entitled xe2x80x9cA 6 um 2 bipolar transistor using 0.25-um process technology for high-speed applicationsxe2x80x9d by T. Hashimoto,T. Kikuchi, K. Watanabe, S. Wada, Y. Tamaki, M. Kondo, N. Natsuaki, and N. Owada of the Hitachi Ltd. Device Development Center, Tokyo, Japan, published in IEEE BCTM 9.1, 0-7803-4497-9/98, 1998 IEEE, the complete disclosure of which is hereby fully incorporated into the present application by reference.
Two types of substrate isolation techniques have heretofore been employed in SOI (such as the bonded SOI BiCMOS process technology available from Hitachi Ltd.). The first is guard rings, and the second is SiO2 trench isolation. Guard rings are substrate contacts that enclose the area to be isolated. Dielectric trench isolation structures provide lateral barriers between circuit elements. These techniques isolate signals and minimize the undesired coupling that would otherwise limit performance for closely spaced adjacent circuit elements.
U.S. Pat. No. 5,661,329 discloses an element separating groove arrangement formed to surround active regions to be formed with a semiconductor element. One disadvantage of this separating groove arrangement is that external RF power can still pass through the separating grooves to the active region. Specifically, the separating groove arrangement described in the ""329 patent appears to be intended primarily for yield improvement and not for RF isolation. The ""329 patent does not appear to address the problem of RF isolation and appears to show no intent to terminate electric fields created by RF power.
Thus, there is a need for an apparatus and method that provides improved RF isolation on SOI process technology.
The present invention provides a semiconductor integrated circuit (IC) device that includes a substrate, an insulating layer formed on the substrate, and additional semiconductor layers formed on the insulating layer. A first isolation trench is formed in the additional semiconductor layers that extends to the insulating layer and that surrounds a first selected surface area of the additional semiconductor layers. A second isolation trench is formed in the additional semiconductor layers that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. A ground conductor couples the guard ring region to a ground node.
The present invention also provides a semiconductor integrated circuit (IC) device that includes a substrate, an insulating layer formed on the substrate, a buried layer formed on the insulating layer, and an epitaxial layer of a first conductivity type formed on the buried layer. A first isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds a first selected surface area of the epitaxial layer. A second isolation trench is formed in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench. A collector is implanted into the epitaxial layer in the guard ring region. A contact is made to the collector, and a conductor connects the contact to a ground node.
The present invention also provides a semiconductor integrated circuit (IC) device that includes a silicon-on-insulator (SOI) substrate having an insulating layer formed on a substrate. A guard ring is formed on a surface of the insulating layer which surrounds a first selected surface area of the insulating layer. The guard ring has a lower buried layer region in contact with the surface of the insulating layer and an upper collector region. First and second oxide filled isolation trenches are formed substantially perpendicular to and in contact with the surface of the insulating layer which sandwich and isolate the guard ring therebetween. A contact is made to the upper collector region of the guard ring, and a conductor connects the contact to a ground node.
The present invention also provides a method of forming a semiconductor integrated circuit (IC) device. The method includes: forming a silicon-on-insulator (SOI) substrate having an insulating layer formed on a substrate; forming a buried layer on the insulating layer; forming an epitaxial layer of a first conductivity type on the buried layer; forming a first isolation trench in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds a first selected surface area of the epitaxial layer; forming a second isolation trench in the epitaxial layer and the buried layer that extends to the insulating layer and that surrounds the first isolation trench and defines a guard ring region between itself and the first isolation trench; implanting a collector into the epitaxial layer in the guard ring region; establishing a contact to the collector; and connecting the contact to a ground node.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.